NXP Semiconductors LPC24XX UM10237 Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Hardware NXP Semiconductors LPC24XX UM10237.
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Nxp semiconductors LPC24XX UM10237 Bedienungsanleitung (792 Seiten)

Marke: Nxp-semiconductors | Kategorie: Hardware | Größe: 4.71 MB |

Inhaltsverzeichnis

LPC24XX User manual

Contact information

1. Introduction

2. How to read this manual

3. LPC2400 features

5. Ordering options

5.3 LPC2468 ordering options

5.4 LPC2470 ordering options

6. Architectural overview

• the standard 32-bit ARM set

• a 16-bit Thumb set

8. On-chip SRAM

9. LPC2458 block diagram

10. LPC2420/60 block diagram

11. LPC2468 block diagram

12. LPC2470 block diagram

13. LPC2478 block diagram

3. Memory maps

4. APB peripheral addresses

5.2 Memory re-mapping

6. Memory mapping control

2. Pin description

3.1 External interrupt inputs

3.2 Reset

DD(DCDC)(3V3)

4. Brown-out detection

2. Oscillators

3.2 PLL (Phase Locked Loop)

3.3 Clock dividers

3.4 Power control

4. Power domains

5. Wakeup timer

5. EMC functional description

Fig 15. EMC block diagram

5.2.2 Memory transaction size

5.4.1 Write buffers

6. Low-power operation

7. Memory bank select

8. Reset

9. Pin description

10. Register description

0xFFE0 8020)

0xFFE0 8024)

(EMCDynamictRP - 0xFFE0 8030)

- 0xFFE0 8038)

0xFFE0 8044)

(EMCDynamictRC - 0xFFE0 8048)

0xFFE0 804C)

0xFFE0 8050)

0xFFE0 8080)

0xFFE0 8100, 120, 140, 160)

0xFFE0 8200, 220, 240, 260)

0xFFE0 8204, 224, 244 ,264)

0xFFE0 8208, 228, 248, 268)

0xFFE0 820C, 22C, 24C, 26C)

0xFFE0 8214, 234, 254, 274)

11. External memory interface

NXP Semiconductors

100

1. How to read this chapter

101

2. Introduction

101

3. Operation

101

4.3 Flash programming Issues

103

6. MAM configuration

104

7. Register description

105

8. MAM usage notes

107

1. Features

109

2. Description

109

3. Register description

109

4. Interrupt sources

116

2. LPC2400 pin packages

120

2.2 LPC2400 208-pin packages

121

6. LPC2420/60/70 boot control

175

5. Register description

178

• For all the other bits:

179

2. Basic configuration

194

3. Features

194

4. Applications

195

5. Pin description

196

6. Register description

196

0x3FFF C0[1/3/5/7/9]0)

205

6.6 GPIO interrupt registers

207

7. GPIO usage notes

209

3. Introduction

211

4. Features

212

5. Ethernet architecture

213

5.2 Example PHY Devices

215

5.3 DMA engine functions

215

5.4 Overview of DMA operation

216

5.5 Ethernet Packet

216

6. Pin description

217

9.1 Overview

247

9.6 Transmit process

252

9.7 Receive process

258

9.8 Transmission retry

264

9.10 Duplex modes

265

• Hash function:

270

• Multicast and unicast

270

9.14 Power management

270

9.15 Wake-up on LAN

271

9.19 Statistics counters

275

9.20 MAC status vectors

275

9.23.1 DMA access

277

9.23.2 Types of CPU access

279

9.23.3 Overall bandwidth

279

• Bus error

287

6.1 AHB interfaces

287

6.4 RAM palette

292

6.5 Hardware cursor

294

CRSR_XY(X)

295

CRSR_XY(Y)

295

6.6 Gray scaler

299

6.10.1 STN displays

300

6.10.2 TFT displays

300

• PCD = 5 (LCDCLK / 7)

306

0xFFE1 0010)

310

0xFFE1 0014)

310

0xFFE1 0C2C)

322

8. LCD timing diagrams

323

9. LCD panel signal usage

325

1. Basic configuration

329

5. Functional description

331

5.1 Analog transceiver

332

5.3 Endpoint RAM (EP_RAM)

332

5.4 EP_RAM access control

332

6. Operational overview

333

7. Pin description

334

12 MHz clock from the USB bus

335

9. Register description

336

9.1 Port select register

337

9.2 Clock control registers

338

ENDPOINT INDEX

350

MPS_EP31

350

9.8 DMA registers

353

10. Interrupt handling

360

13. Slave mode operation

373

14. DMA operation

374

14.4.8 DD_retired

378

14.4.9 DD_status

378

14.4.10 Packet_valid

378

14.4.6 DMA_buffer_length

378

14.4.7 DMA_buffer_start_addr

378

15.1 Bulk endpoints

386

15.2 Isochronous endpoints

388

3. Interfaces

390

3.2 Software interface

391

4. Architecture

394

5. Modes of operation

395

6. Pin configuration

395

Bit Symbol Description Reset

402

7.16 Interrupt handling

410

8. HNP support

411

9.2 Power-down mode support

421

TXD0, TXD2, TXD3 Output

423

Serial transmit data

423

4. Register description

424

435

5. Architecture

441

2. Features

443

3. Pin description

444

DLAB = 0)

448

4.9 Auto-flow control

454

4.10 Auto-CTS

455

4.15 Auto-baud

459

3. CAN controllers

467

TD1, TD2 Output

468

To CAN transceivers

468

6.3 Transmit Buffers (TXB)

470

6.4 Receive Buffer (RXB)

470

31 24 23 16 15

471

10 9 8 7 0

471

8. Register description

473

0xE004 8004)

476

0xE004 8008)

478

0xE004 800C)

480

0xE004 8010)

484

0xE004 8014)

485

0xE004 8018)

487

0xE004 8020)

489

0xE004 8024)

490

0xE004 8028)

490

0xE004 802C)

491

9. CAN controller operation

494

10. Centralized CAN registers

495

11. Global acceptance filter

497

12. Acceptance filter modes

497

14. ID look-up table RAM

498

0xE003 C004)

502

0xE003 C008)

502

0xE003 C010)

503

15.8 Status registers

504

FCANIC1 - 0xE003 C028)

505

17. FullCAN mode

507

17.1 FullCAN message layout

509

17.2 FullCAN interrupts

511

18.6 Configuration example 6

520

FullCAN not activated

521

18.7 Configuration example 7

522

3. SPI overview

526

4. SPI data transfers

526

• When data is sampled

527

5. SPI peripheral details

528

5.3 Slave operation

529

5.4 Exception conditions

529

8. Architecture

534

3. Description

536

4. Pin descriptions

537

5. Bus description

537

5.2 SPI frame format

538

• SSEL is forced HIGH

539

• CS is forced HIGH

543

0xE003 0004)

546

SSP1RIS - 0xE003 0018)

549

SSP1MIS - 0xE003 001C)

549

0xE003 0020)

550

SSP1DMACR - 0xE003 0024)

550

MCICLK Output Clock output

551

5. Functional overview

552

Fig 106. MCI adapter

553

5.3.1 Adapter register block

554

5.3.2 Control unit

554

5.3.3 Command path

554

CmdTimeOut Response timeout

557

5.3.8 Data counter

559

E008 C01C and E008 C020)

566

3. Applications

572

4. Description

572

C operating modes

574

6.2 Master Receiver mode

575

6.3 Slave Receiver mode

576

6.4 Slave Transmitter mode

577

7.2 Address Register I2ADDR

579

7.3 Comparator

579

7.4 Shift register I2DAT

579

7.6 Serial clock generator

580

7.7 Timing and control

580

0xE005 C000, 0xE008 0000)

582

9. Details of I

586

9.1 Master Transmitter mode

587

Value- 10001-

588

9.4 Slave Transmitter mode

593

9.5 Miscellaneous states

599

9.11 Bus error

601

9.12.1 Initialization

602

10. Software example

603

C interrupt routine

604

10.5 Non mode specific states

604

10.6 Master states

604

10.8 Master Receive states

606

10.9 Slave Receiver states

607

7. FIFO controller

618

0xE007 0000, 0xE007 4000)

624

0xE007 0004, 0xE007 4004)

624

0xE007 0070, 0xE007 4070)

625

0xE007 0014, 0xE007 4014)

627

0xE007 0028, 0xE007 4028)

628

0xE007 003C, 0xE007 403C)

629

7. Example timer operation

630

4. Pin description

637

5. PWM base addresses

637

0xE001 8000)

639

PWM1TCR 0xE001 8004)

640

PWM1CTCR 0xE001 8070)

641

PWM1MCR 0xE001 8014)

641

PWM1CCR 0xE001 8028)

643

0xE001 804C)

644

6.1 RTC interrupts

650

6.4 Time Counter Group

654

6.5 Alarm register group

655

6.6 Alarm output

656

6.7 RTC clock generation

656

7. RTC usage notes

659

8. Battery RAM

660

2. Applications

662

0xE000 0010)

665

5. Block diagram

666

0xE003 402C)

672

6. Operation

673

5. Operation

675

2. Flash boot loader

676

5. Description

676

5.2 Communication protocol

678

6. Boot process flowchart

680

7. Sector numbers

681

8. Code Read Protection (CRP)

682

9. ISP commands

683

9.3 Echo <setting>

685

10. IAP commands

690

10.2 Copy RAM to Flash

693

10.3 Erase Sector(s)

694

10.4 Blank check sector(s)

694

10.8 Reinvoke ISP

695

10.9 IAP Status Codes

696

4.2 Communication protocol

698

5. Boot process flowchart

700

6. ISP commands

701

6.3 Echo <setting>

702

6.10 ISP Return Codes

705

7. IAP commands

706

7.4 Reinvoke ISP

709

7.5 IAP Status Codes

709

3. Features of the GPDMA

711

4. Functional overview

712

4.2.1 AHB Slave Interface

713

SSP0 Tx 0 0 -

717

SSP0 Rx 1 1 -

717

SSP1 Tx 2 2 -

717

5. Programming the GPDMA

718

6.1 General GPDMA registers

721

DMACC1SrcAddr - 0xFFE0 4120)

727

7. Address generation

733

8. Scatter/Gather

733

9. Interrupt requests

735

10. GPDMA data flow

736

11. Flow control

739

5. JTAG function select

742

7. Block diagram

742

3.1 RealMonitor components

749

3.2 How RealMonitor works

750

Undef 48

751

Prefetch Abort 16

751

Data Abort 16

751

4.10 RMTarget initialization

753

4.11 Code example

753

5. RealMonitor build options

756

1. Abbreviations

759

2. Legal information

760

3. Tables

761

4. Figures

773

5. Contents

775

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NXP Semiconductors LPC24XX UM10237 Handbücher

Nxp semiconductors LPC24XX UM10237 Bedienungsanleitung (792 Seiten)

Inhaltsverzeichnis

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